Low temperature process for polysilazane oxidation/densification

ABSTRACT

Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. Ser. No. 11/321,511, filedDec. 29, 2005, now U.S. Pat. No. 7,557,420, which is a divisional ofU.S. Ser. No. 10/883,191, filed Jul. 1, 2004, now U.S. Pat. No.7,521,378.

FIELD OF THE INVENTION

The invention relates generally to semiconductor processing methods offorming and utilizing insulative materials for electrical isolation inintegrated circuits, and more particularly to processes for forminginsulating films from polysilazane coatings.

BACKGROUND OF THE INVENTION

In the fabrication of semiconductor integrated circuits, semiconductorelements are integrated and laid out within a small area on a chiprequiring the devices to be placed in close proximity to each other.With the continuing decrease in the dimensions and spacing of devices onintegrated circuits (ICs), insulative materials are deposited toelectrically isolate the various active components such as transistors,resistors and capacitors. Isolation insulative materials are typicallymade of silicon dioxide (SiO₂).

For example, interlayer dielectric (ILD) or pre-metal dielectric (PMD)layers isolate structures from metal interconnect layers, which mayrequire filling narrow gaps having high aspect ratios (ratio of depth towidth) of five or greater. Insulative structures such as shallow trenchisolation (STI) regions are also formed in recesses (trenches) withinthe substrate between components. Such trenches can have a width asnarrow as 0.01 to 0.05 micron (μm) or smaller, and filling such narrowfeatures can be difficult. In addition, the dielectric material must beable to withstand subsequent processing steps such as etch and cleaningsteps.

Dielectric materials are typically deposited by chemical vapordeposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).For example, in a typical STI method, a trench is etched into a siliconsubstrate, and the trench is filled by CVD of an oxide such as silicondioxide (SiO₂) as a conformal layer. In the trenches, the conformallayers of oxide are initially formed on the sidewalls and grow in sizeoutward into the center of the trench to where the oxide layers meet.With high aspect ratio features, the width becomes narrower while thedepth becomes much greater, it is difficult to form a void-free orseam-free gap fill using standard CVD or PECVD techniques.

High temperature processing after formation of an oxide insulatinglayer, such as an annealing or high temperature densification step, cancause a loss of oxygen from the dielectric material resulting inelectrically leaking films. To reduce such effects, dielectric materialshave been CVD deposited from ozone-enhanced tetraethylorthosilicate(TEOS). Although demonstrating good filling properties, such a processis slow and not cost effective.

Flowable materials, such as spin-on dielectrics (SODs), spin-on glasses(SOGs), and spin-on polymers, such as silicates, siloxanes, silazanes orsilisesquioxanes, have been developed that generally have good gapfilling properties. A silicon oxide film is formed by spin-coating aliquid solution of the silicon-containing polymer onto a surface of asubstrate, baking the material to remove the solvent, and then thermallyoxidizing the polymer layer in an oxygen, or steam, atmosphere at anelevated temperature of up to about 1000° C. A drawback is that hightemperature treatments can degrade other structures such as aluminum orother metal wiring layer that have a low thermal tolerance. Anotherdrawback of current methods is the high cost and time required forprocessing. Such products may require limited thermal budget processingwhere extensive densification can hurt device parameters. Consequently,lower temperature processing techniques are desired.

Therefore, it would be desirable to provide a process that overcomessuch problems.

SUMMARY OF THE INVENTION

The present invention provides methods of forming and treatinginsulative materials, and devices and systems that incorporate suchinsulative materials.

In one aspect, the invention provides a process of forming a dielectric(a silicon oxide) film or layer on a semiconductor device. In oneembodiment, the silicon oxide layer is formed from a solution comprisinga silicon-containing polymer, preferably polysilazane, in which thepolymer solution is spin-coated onto a substrate, the solvent is removedto form a solid-phase layer, and the polymer layer undergoes acompositional change caused by a process of wet chemical oxidation at alow temperature of less than about 100° C. to form a silicon oxidelayer.

The process can be utilized to form a variety of insulating structuresand devices. For example, the process is useful in forming a shallowtrench isolation (STI) device, an interlevel insulating layer, amongother structures. The spin-on polymer solution can be deposited tosubstantially fill a high aspect ratio trench or other opening or gapwithout leaving voids, and the post deposition treatment of lowtemperature, wet oxidation is then conducted to oxidize the material toform a silicon oxide layer.

In another aspect, the invention provides a silicon oxide layer or fillsituated on a substrate, which comprises a spin-on silicon materialtreated by low temperature, wet oxidation processing (e.g., deionizedwater/ozone) such that the material is highly oxidized and essentiallylacks hydrogen and nitrogen elements, and contains substantially novoids. The silicon oxide layer or fill can be situated, for example,within a high aspect ratio opening such as a shallow trench isolation(STI) structure, as an interlevel insulation layer, among otherapplications.

Also provided according to the invention is a semiconductor devicecomprising a substrate and a silicon oxide layer prepared according tothe process of the invention, for example, a layer of polysilazanemodified by low temperature, wet oxidation to a silicon oxide layer. Theoxide layer can comprise a trench isolation structure, for example.

In yet another aspect, the invention provides an integrated circuitdevice. In one embodiment, the integrated circuit device supported by asubstrate, comprises a silicon oxide layer disposed on the substrate,for example, as a fill within an opening such as a shallow trenchisolation structure, the silicon oxide layer comprising a flowablesilicon-comprising material (e.g., a spin-on polysilazane) treated bylow temperature, wet oxidation processing (e.g., deionized water/ozone).The integrated circuit device comprising the low temperature, wetoxidation-treated silicon oxide layer can be incorporated into a die ofa circuit module, for example, which can be incorporated into anelectronic system.

Films prepared according to the invention are particularly useful infilling narrow gaps and openings less than about 100 nm in width,particularly openings less than about 50 nm in width. The silicon oxidefilms of the invention are advantageously used as pre-metal dielectric(PMD) interlayers and as shallow trench isolation (STI) structures.

The present silicon oxide material is useful for filling narrow gaps ina PMD interlayer and for filling trenches in shallow trench isolationstructures. PMD interlayers may include polysilicon gates and a barrierlayer on a substrate, with narrow gaps between the gate structures. Thematerial of the invention can be deposited and processed to fill spacesbetween the structures with a silicon oxide insulating fill. The processin accordance with the invention achieves a solid, void-free siliconoxide fill or layer having a high oxygen content that can be easilyprocessed and will maintain its integrity in subsequent processingsteps.

Advantages of the present procedure include low cost, simplicity, batchprocessing, and a low thermal budget, among others. The procedure can beused for the oxidation and densification of polysilazane films andspin-on-dielectric (SOD) films having a lower oxygen content thansilicon dioxide (SiO₂) or hydroxyl content to produce a film that hasimproved uniform etch properties. The low temperature process (T<100°C.) is particularly useful for deep trench applications (1000-3000 Å orgreater) in the fabrication of Flash memory, FINFET, RAD, SDRAM, PC-RAM,and dense DRAM structures. The process avoids the use of hightemperatures (i.e., 700-800° C.), which can damage other features thatare present on the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings, which are forillustrative purposes only. Throughout the following views, thereference numerals will be used in the drawings, and the same referencenumerals will be used throughout the several views and in thedescription to indicate same or like parts.

FIGS. 1-6 are diagrammatic cross-sectional views of a fragment of asemiconductor wafer substrate at sequential processing steps showingfabrication of a trench isolation according to an embodiment of themethod of the invention. FIGS. 1-3 illustrate processing steps forming atrench in a surface of the substrate. FIG. 4 shows deposition of apolymer (e.g., polysilazane) solution on the substrate and into thetrench. FIG. 5 depicts treating the polysilazane layer to form asolid-phase layer. FIG. 6 illustrates a wet oxidation processing step tomodify the polysilazane layer to a silicon oxide layer. FIG. 6Aillustrates another embodiment of a structure resulting from a wetoxidation processing step.

FIGS. 7-9 are diagrammatic cross-sectional views of a fragment of asemiconductor wafer substrate at sequential processing steps in thefabrication of a trench isolation structure according to anotherembodiment of the method of the invention involving the processing of athin polysilazane layer on the substrate.

FIGS. 10-12 are diagrammatic cross-sectional views of the semiconductorwafer substrate shown in FIG. 6A at subsequent processing stepsinvolving an etch back step and a low temperature/wet oxidationaccording to the invention, and the coating and processing of anadditional polysilazane layer to increase the thickness of the siliconoxide layer to form a trench isolation structure.

FIG. 13 illustrates a cross-sectional view of the substrate shown inFIG. 12 at a subsequent processing step involving a steam treatment toconvert the polysilazane material to silicon oxide throughout the depthof the layer.

FIG. 14 is an illustrative cross-sectional view of the semiconductorwafer of FIG. 13 at a subsequent processing step of a CMP or etch backto form a trench isolation structure.

FIG. 15A-15E are diagrammatic cross-sectional views of a fragment of asemiconductor wafer substrate at sequential processing steps showingfabrication of a trench isolation structure according to anotherembodiment of the method of the invention involving repeated depositionof a thin polysilazane coating and wet oxidation to form a silicon oxidefill within the trench.

FIG. 16 is a schematic diagram of an embodiment of a spin and spraysystem for delivering an ozone-rich water solution onto a substrateaccording to the invention.

FIGS. 16A and 16B are a partial schematic diagrams of other embodimentsof a spin and spray system shown in FIG. 16.

FIG. 17 is a schematic diagram of an embodiment of an immersion systemfor applying an ozone-rich water solution onto a substrate according tothe invention.

FIGS. 18 and 19 are diagrammatic cross-section views of a fragment of asemiconductor wafer substrate at sequential processing steps showingfabrication of an interlevel dielectric layer according to anotherembodiment of the method of the invention.

FIG. 20 is a block diagram of a circuit module according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention will be described generally with reference to the drawingsfor the purpose of illustrating the present preferred embodiments onlyand not for purposes of limiting the same. The figures illustrateprocessing steps for use in the fabrication of semiconductor devices inaccordance with the present invention. It should be readily apparentthat the processing steps are only a portion of the entire fabricationprocess.

In the context of the current application, the term “semiconductorsubstrate” or “semiconductive substrate” or “semiconductive waferfragment” or “wafer fragment” or “wafer” will be understood to mean anyconstruction comprising semiconductor material, including but notlimited to bulk semiconductive materials such as a semiconductor wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure including, but not limited to, the semiconductive substrates,wafer fragments or wafers described above.

The following description with reference to the figures providesillustrative embodiments of the formation of a shallow trench isolation(STI) structure and an insulating layer between two materials(interlevel dielectric layer) formed in accordance with the presentinvention. Such description is only for illustrative purposes and thepresent invention can be utilized to provide a silicon oxide (silicondioxide) layer in other constructions and devices. The present inventionis not limited to the described illustrative devices.

FIGS. 1-6 illustrate a method for forming a dielectric layer accordingto one embodiment of the present invention, in forming a shallow trenchisolation (STI) structure, which may be employed for electricallyisolating devices in an integrated circuit from one another. By way ofexample, the STI structure can be formed relative to transistor gateconstructions and adjacent transistor source/drain regions with thesubstrate.

Referring to FIG. 1, a wafer fragment 10 is shown at a preliminaryprocessing step. The wafer fragment 10 in progress can comprise asemiconductor wafer substrate or the wafer along with various processlayers formed thereon, including one or more semiconductor layers orother formations, and active or operable portions of semiconductordevices. A semiconductor device can comprise a transistor, capacitor,electrode, insulator or any of a variety of components commonly utilizedin semiconductor structures.

The wafer fragment 10 is shown as comprising a semiconductor substrate12 having a thin dielectric (SiO₂) layer 14 of about 8-20 nm formedthereon, which serves as a pad oxide. Dielectric layer 14 can be formed,for example, by thermal oxidation of substrate 12, by CVD deposition,sputtering, and the like. Optionally, a thicker second dielectric layer16, preferably a silicon nitride (Si₃N₄) layer having a thickness ofabout 40-200 nm, can be formed over the SiO₂ layer 14 by CVD or otherdeposition technique, to provide an oxidation and CMP hard mask layer. Aphotoresist mask 18 is applied and patterned using a lithographicpatterning technique, and the SiO₂ layer 14, Si₃N₄ layer 16, andsubstrate 12 are dry etched to form an opening or recess such as ashallow trench 20 in the substrate 12 for device isolation. For example,the trench 20 can have a width of about 0.1 μm and a depth of about 0.5μm, with an aspect ratio of 5 (=0.5/0.1). Trench 20 includes sidewalls22 and bottom surface 24. The trench 20 can have sloped or taperedsidewalls 22 or vertical sidewalls formed by an anisotropic etch. Thephotoresist mask 18 is then removed to form a trenched structure, asshown in FIG. 2.

After stripping the photoresist and cleaning the trenched structure, athin silicon oxide (SiO₂) layer 26 can then be formed on the sidewalls22 and bottom surface 24 of the trench 20, for example, by thermaloxidation, high-pressure oxidation, or high density plasma CVD using asilane-based material or TEOS, for example, as depicted in FIG. 3.Generally, the silicon oxide layer 26 is about 50 angstroms (Å) to about500 Å thick. Optionally, as illustrated, a thin silicon nitride barrierlayer (liner) 28 can be formed over the silicon oxide layer 26 to athickness of about 100 Å or less, for example, by CVD using SiH₄ and NH₃as source gases.

As shown in FIG. 4, a spin-on silicon-containing polymer solution iscoated on the substrate 12 and into the trench 20 to form a siliconpolymer layer 30 a. Typically, the silicon-containing polymer layer isformed on the substrate by spin coating or a “spin-on-glass (SOG)”process, although other methods such as flow coating, dipping orspraying can be used.

In a preferred embodiment, the silicon-containing polymer is depositedas a coating from a polysilazane solution in an organic solvent by spincoating (or SOG process) to fill a predetermined portion or the entiretrench. Polysilazanes contain Si_(x)N_(y)H_(z) type units in which theSi atoms are in a “reducing environment” in —Si—NH— bonds. Examples ofsuitable polysilazanes that can be used include hexamethyldisilazane(HMDS), tetramethyldisilazane, octamethylcyclotetrasilazine,hexamethylcyclotrisilazine, diethylaminotrimethylsilane, anddimethylaminotrimethylsilane, among others, with perhydro-polysilazanebeing preferred. Polysilazane material cannot be etched or processedreasonably without modification, and even 500:1 HF will etch itnon-uniformly with greater than 1000 Å/minute etch rate. Oxidation of Nbonds is required to transform this material to SiO₂.

In forming a layer on the substrate, a solution of polysilazane isdropped onto a surface of a silicon substrate or layer on the substratewhile rotating the substrate on a horizontal plane to form auniformly-coated film of the solution on the entire surface of thesubstrate or layer due to the centripetal force applied to the substrate(e.g., wafer). The thickness of the polysilazane coating layer 30 a canbe controlled by means of the concentration of the coating solution andthe speed of rotation of the substrate. The coating layer 30 a generallyranges in thickness from about 30 nm to about 500 nm.

The polysilazane solution is prepared with a compatible organic solventcommonly used in coating solutions of spin-on polymers. Suitable organicsolvents include, for example, dibutyl ether (DBE), toluene, xylene, andthe like. The concentration of the polysilazane in solution can bevaried to adjust the consistency (i.e., viscosity) of the solution andthickness of the coating. A solution containing between about 4% toabout 30% by weight polysilazane can be used and, more preferably, asolution containing about 8% to about 20% by weight polysilazane.Additional minor amounts of additives such as surfactants and binderscan be included in the solution.

The conditions under which the polysilazane solution is spin-coated ontothe surface of the substrate 12 include a substrate temperature of about18° C. to about 25° C., and a typical spin rotation of about 500 rpm toabout 6,000 rpm for a rotation time of about 2 seconds. A typical layeris about 50 nm to about 500 nm thick.

As depicted in FIG. 5, after coating, the substrate is heated to dry thepolysilazane coating layer 30 a by removing the organic solvent andproduce a solid-phase polysilazane layer 30 b. The coated film can bedried, for example, by baking the substrate on a hotplate at about 75°C. to about 350° C., preferably at about 150° C. to about 200° C.,typically for about 1 to about 3 minutes. The resulting “as spun” or“spin-filled” polysilazane film without densification has non-uniformwet etch properties, typically exhibiting a very high etch rate influoride-based etch chemistries with significant non-uniformity that maybe related to redox sensitivity and/or high selectivity betweendifferent regions of the layer.

Referring now to FIG. 6, to increase its etch resistance in a subsequentprocessing step, the dried polysilazane coating 30 b is treated (cured)to modify it to a silicon oxide layer 30 c and provide a densifiedlayer. According to the invention, a controlled low temperature, wetchemical oxidation of the polysilazane coating layer 30 b is conductedto modify the chemical composition to form an —Si—O—Si—network structureand substantially fully oxidize the polysilazane layer 30 b into anoxide of silicon. Preferably, the chemical transformation decreases thenitrogen (N%) and hydrogen (H%), and the resulting oxidation increasesthe oxygen (O%) content of the layer close to a SiO₂ composition.

In this step, the polysilazane layer 30 b is subjected to a wetoxidation chemistry to oxidize the polysilazane groups Si_(x)N_(y)H_(z)of the polysilazane material 30 b by replacing nitrogen and hydrogenatoms with oxygen atoms to form the layer into an oxygen rich material30 c, i.e., a silicon oxide, and primarily silicon dioxide (SiO₂). Thepolysilazane-based silicon oxide is preferably treated by a wetoxidation in the presence of ozone (O₃), or alternatively in a StandardClean 1 (SC1; a dilution of NH₄OH/H₂O₂) or a Standard Clean 2 (SC2; adilution of HCl/H₂O₂), such that more than about 80% of N and H arereplaced in the upper 200-1500 Å of the polysilazane layer, as can bedetermined by XPS% atomic analysis and/or SIMS depth profiling analysis.

The replacement of Si—N, N—H and Si—H bonds with —Si—O—Si— bondsdecreases the etch rate by different etch chemistries and improvesuniformity of the etch. This modification results in a layer that can beuniformly, reproducibly, and controllably etched back to shape thestructure, for example, by applying a fluoride-based etchant whereby thestructure is etched at an etch rate of less than about 200 Å/minute,preferably in the about 10-20 Å/minute range, similar to thermal oxide,as can be demonstrated by SEM imaging to show a relatively uniform etchback. Exemplary fluoride-based etchants include a fluoride-containing,non-aqueous, isopropyl alcohol (IPA)-based etch solution, a non-aqueousNH₄F:HF etch solution, and a solution comprising about 0.01-2% HF.Typically, the polysilazane layer 30 b exhibits a volume shrinkage of anabout 10% to about 15% decrease in thickness during the oxidationprocessing to form the silicon oxide layer 30 c.

Referring now to FIG. 6A, in a high aspect ratio structure such as atrench, it can be difficult to diffuse oxygen into the polysilazanelayer in the deeper part of the structure. With the wet oxidationprocess, an upper portion of the polysilazane layer 30 a is oxidizednearly quantitatively to silicon dioxide (SiO₂) with little residual Nbeing left in the oxidized portion. This tends to prevent oxygen fromdiffusing into the underlying region beyond the fully oxidized layer(zone) such that the polysilazane layer 30 b in a deeper part of thetrench is oxidized more restrictively (partially oxidized) where theoxygen (O) concentration is decreasing and the nitrogen (N)concentration is increasing. Thus, the formation of a silicon oxidelayer is self-limiting.

FIG. 6A depicts the deposition and oxidation of a medium coating ofpolysilazane of about 200-300 nm thick on the substrate. Anotherembodiment is depicted in FIGS. 7-9 illustrating the deposition of athin coating of polysilazane 30 a′ of about 50-100 nm thick, the dryingof the layer 30 a′ to a solid-phase layer 30 b′, and a lowtemperature/wet oxidation forming a top layer of silicon oxide 30 c′.

Oxygen penetration into the polysilazane layer 30 b, 30 b′ is typicallyto a depth of about 500-1500 Å (50-150 nm), and preferably to a depth ofat least about 900 Å (90 nm) of a 50-5000 Å (50-500 nm) thick layer,with a decreasing oxygen profile thereafter. If the polysilazane layeris not completely oxidized, hydrogen and nitrogen remain in the materialresulting in a porous layer, which is unstable and unreliable in asubsequent wet etch process step, which can be used to shape the layerto form a recessed trench fill, for example.

As depicted in FIGS. 6A and 9, where the thickness of the silicon oxidelayer 30 c, 30 c′ is not adequate for it to function as a STI structureor for interlayer isolation, and the thickness of the layer 30 c, 30 c′cannot be increased by further wet oxidation processing, the structurecan be further processed to increase the thickness of silicon oxidewithin the trench.

For example, with respect to the structure depicted in FIG. 6A, in anoptional step, a CMP or etch-back (wet or dry) can be conducted toremove or recess about 20-100 nm of a top portion 30 c(1) of the siliconoxide layer 30 c as shown in phantom (by dashed line - - -) in FIG. 10.The silicon oxide layer 30 c can be etched, for example, by applicationof a wet etch solution for a controllable etch back, such as anon-aqueous fluoride-containing etch solution, an NH₄F-based etchreagent, or a dilute solution of hydrofluoric acid (HF), or, althoughnot preferred, by means of a reactive ion etching (RIE) process using anetch gas such as CF₄ and CHF₃.

Referring now to FIG. 11, a low temperature/wet oxidation step can thenbe performed to oxidize an additional portion of the polysilazane layer30 b to increase the depth (thickness) of the insulating silicon oxidelayer 30 c within the trench.

An additional thin coating of polysilazane can then be applied andprocessed by wet oxidation according to the invention to a silicon oxidelayer 30 c to increase the overall thickness of the silicon oxide layer,as shown in FIG. 12.

As a wet oxidation treatment is typically limited to oxidizing the topportion of the layer, in an optional processing step, a steam treatmentcan be utilized to provide a substantially complete conversion of thepolysilazane (or SOD) to SiO₂ throughout the depth of the layer, asdepicted in FIG. 13. The steam treatment comprises, for example,reacting hydrogen (H₂) and oxygen (O₂) together to form water vapor thatis then introduced into a reaction chamber for contact with thepolysilazane (or SOD) layer, or reacting the H₂ and O₂ together directlyat the surface boundary layer. The processing temperature is generallyabout 125° C. to about 1,100° C., and the process duration is about 10minutes to 120 minutes.

After formation, the silicon oxide layer 30 c can be planarized by CMP,etch back, and the like, as shown in FIG. 14 to complete a trenchisolation structure 32 by removing a portion of the silicon oxideisolation layer 30 c filling the trench to be level with the substrate12. A gate or other structure can then be fabricated according to knowntechniques.

Thus, an exemplary shallow trench isolation structure 32 depicted inFIG. 14, includes substrate 12, pad oxide layer 14, hard mask (Si₃N₄)layer 16, shallow trench 20, silicon oxide layer 26, optional siliconnitride liner 28, and polysilazane-based silicon oxide fill layer 30 c.

The steps of depositing a polysilazane coating and conducting the lowtemperature/wet oxidation step, can be repeated and/or combined withoptional processing steps, such as an etch back step, CMP, and/or steamtreatment, for example, to achieve the desired structure of a siliconoxide layer within the trench.

For example, as illustrated in FIGS. 15A-15C, in forming an STIstructure, a thin coating of polysilazane solution can be spin coated onthe surface of the substrate 12 to partially fill a trench 20, thepolysilazane layer (30 a) can be baked to remove the solvent, the driedlayer (30 b) treated by the low temperature/wet oxidation to convert itto a silicon oxide layer 30 c, and then the steps can be repeated tocoat additional layers of polysilazane thereon, each of which are driedand wet oxidized according to the invention, to increase the totalthickness of silicon oxide 30 c within the trench. As furtherillustrated in FIGS. 15D and 15E, the structure can also be steamtreated to oxidize the trench structure throughout the depth, and thenplanarized to form the trench isolation structure 32.

The following TABLE provides several non-limiting examples ofintegration schemes that can be utilized according to the invention.

Example 1 Example 2 Example 3 Example 4 Apply thin coat Apply mediumcoat Apply medium coat Apply thick coat (50-100 nm) of (200-300 nm) of(200-300 nm) of (300-500 nm) of polysilazane polysilazane polysilazanepolysilazane DI/ozone treatment DI/ozone treatment DI/ozone treatmentSteam treatment Apply thin coat Apply thin coat Etch (dry or wet) CMP(50-100 nm) of (50-100 nm) of polysilazane polysilazane DI/ozonetreatment Steam treatment Apply thin coat DI/ozone treatment (50-100 nm)of polysilazane Apply thin coat CMP DI/ozone treatment Gate sequence(50-100 nm) of polysilazane Steam treatment DI/ozone treatment Applythin coat (50-100 nm) of polysilazane CMP Gate sequence Steam treatmentGate sequence CMP Gate sequence

Thus, the coating step and low temperature, wet oxidation step, withoptional processing steps, can be conducted as desired to produce anoptimal silicon oxide structure.

The low temperature/wet oxidation step can be performed at variouspoints of fabrication where a processing step such as an etch back,patterning, or planarization (CMP) is performed that exposes anundensified polysilazane material layer (or dielectric, e.g., SOD,having a lower oxygen content than SiO₂), which can be oxidizedaccording to the process of the invention.

Suitable wet chemistries that can be used to modify the polysilazanelayer include a deionized water and ozone (DI/O₃) treatment, and/orStandard Clean 1 (SC1) consisting of a dilution of ammoniumhydroxide/hydrogen peroxide (NH₄OH/H₂O₂) followed by a deionized (DI)water rinse (about 20-30 minutes at about 55-75° C.), or a StandardClean 2 (SC2), which is a hydrochloric acid/hydrogen peroxide (HCl/H₂O₂)solution followed by a DI water rinse, with a DI/O₃ treatment beingpreferred and more controllable to oxidize polysilazane.

In one embodiment, the dried polysilazane layer 30 b is exposed to anoxygen source in a spin and spray process in which the wafer is spun ata desired velocity while spraying a thin layer of water, preferably lessthan about 1 mm thick, onto the surface in an oxygen-enriched ambient.In a preferred embodiment, ozone (O₃) is utilized, but the oxygenambient can also comprise oxygen (O₂), NO₂, N₂O, and the like, alone orpreferably in combination with ozone. The water is maintained as a thinlayer on the surface of the wafer so as to facilitate the movement anddiffusion of oxygen into the polysilazane material layer 30 b.

By way of example as illustrated in FIG. 16, the wafer 10 can bepositioned in a reaction chamber 34 having an array of spray nozzles 36for dispensing a spray of deionized (DI) water 38 through an ozone (O₃)ambient gas 40 that is continuously flowed through a gas inlet 42 intothe chamber, to deposit a thin layer of ozone-rich deionized water 38onto the surface of the wafer 10 and the polysilazane layer whilerotating the wafer 10 using a spin tool 44. Ozone gas can be fed throughinlet 42 into the chamber to provide an ozone concentration within thechamber 34 that is preferably at about 50% to about 100% of thesaturation level at the process temperature that is utilized (saturationin water being about 12 ppm at 30° C.). The ozone concentration in thereaction chamber 34 can range from about 0.01 ppm to about 1,000 ppm,preferably about 0.1 ppm to about 100 ppm, preferably about 1 ppm toabout 12 ppm. An exemplary flow rate of ozone into the chamber is about10 sccm to about 1,000 sccm. Preferably, the ozone/water solutiondeposited onto the wafer is a supersaturated solution whereby the watercontains ozone above the water's normal ozone concentration capacity.The water can be applied using a steady stream or by pulse spraying.

In another embodiment depicted in FIG. 16A, ozone gas 40 can be fedthrough an inlet 42 a directly into water inlet 46 to create a watermixture solution 48 containing the ozone at a saturation level of about50% to about 100% (or about 4 ppm to about 15 ppm ozone) depending onthe process temperature, which is then sprayed onto the wafer. In yetanother embodiment, shown in FIG. 16B, the ozone gas 40 can be fedthrough an inlet 42 a into the water inlet 46 and also directly into thechamber 34 through an inlet 42.

The reaction chamber, wafer and water temperatures can be maintained atroom ambient temperature of about 20-30° C. or less, to up to about 100°C., preferably at about 70-90° C. The wafer can be heated for example,on a hot plate, which can be part of the spin tool 44. A preferredpressure of the reaction chamber is atmospheric (˜1 atm) (room ambient).

The wafer 10 is rotated at a velocity that is adequate to maintain auniformly thin layer of ozone-rich water on the surface of the wafer tofacilitate transport (diffusion) of ozone to the polysilazane layer onthe wafer. The velocity of the spinning wafer controls the thickness ofthe layer of water on the surface of the wafer, at least in part. Therotation velocity (spin rate) can range from about 10 revolutions perminute to about 1,000 revolutions per minute (rpm), and is preferablyabout 50 rpm to about 600 rpm.

The wet oxidation of the polysilazane layer tends to produce a virtuallyself-limiting thickness growth or transformation of polysilazane layer30 b to a silicon oxide layer 30 c since ozone is not capable ofadequately diffusing through the growing silicon oxide layer to reactwith the underlying polysilazane layer. Thus, time is not a verycritical factor in the processing of the polysilazane layer. Dependingon the kinetics of the oxidation process, the processing time can rangefrom a few seconds to several hours. Exemplary processing times areabout 60 minutes to oxidize a 700-1000 Å (70-100 nm) thick polysilazanelayer to SiO₂, and up to 8 hours to partially oxidize a 2000Å (200 nm)thick layer.

Thickness of the silicon oxide layer generally increases over time. Apreferred processing time is about 10 minutes to about 100 minutes. Theultimate thickness of a silicon oxide layer 30 c produced by theoxidation process step is typically about 500 Å to about 2000 Å (about50-200 nm). Chemical bonding information and oxidation depth measurementcan be evaluated by XPS % atomic analysis and SIMS depth profilinganalysis showing an oxygen profile of the film (i.e., decrease innitrogen (N%), increase in oxygen (O%), with the surface composition anda depth to about 50-150 nm showing nearly two O atoms per Si atom.

In another embodiment, a pressurized system can optionally be utilizedin order to process the polysilazane layer at a higher temperature. Forexample, the dried polysilazane layer 30 b can be exposed to steam inthe presence of ozone at a temperature of about 100-200° C. and apressure of about 0.5-20 atm to produce the silicon oxide layer 30 c.The exposure to the steam is such that a thin layer of water is formedon the surface of the polysilazane layer to facilitate diffusion ofozone into the layer. In another embodiment of such a system, thepolysilazane layer 30 b can be wet oxidized in the presence of ozone ata temperature of about 100-200° C. and a pressure of about 0.5-20 atm toproduce the silicon oxide layer.

Referring now to FIG. 17, in another embodiment of a method according tothe invention, the wafer 10 can be immersed in a water bath or immersiontank 50 containing ozone-enriched deionized water mixture solution 48such that the water is in contact with the polysilazane layer 30 b onthe wafer 10. Preferably, the water mixture solution 48 contains about2-15 ppm ozone (O₃), preferably an amount of ozone at or above thesaturation point (i.e., 12 ppm ozone at 30° C.). The water temperaturecan be maintained at room ambient temperature of about 20-30° C., orless, to up to about 100° C., preferably at about 90° C.

For example, deionized water 38 can be introduced through water inlet 52into a mixing apparatus or bath/tank 50, and ozone gas 40 can becontinuously injected through gas inlet 54 directly into the water 38 ata predetermined pressure and flow rate. The wafer 10 is then immersedinto the deionized water/ozone mixture 48. The wafer can be mounted in acarrier 56 and/or a device that functions to rotate or move the waferwithin the water for continuous movement and contact with theozone/water solution.

In yet another embodiment, ozonated water can be introduced throughwater inlet 52, with the additional injection of ozone into the waterbeing employed as needed, to provide an O₃ level in the water mixture 48at about 2-15 ppm O₃, preferably an O₃ level at or above the saturationpoint.

Insulating interlayer structure.

FIGS. 18 and 19 illustrate another embodiment of a method for forming adielectric layer, an insulating interlayer, that can be formed on thesurface region of a silicon substrate over semiconductor elements, suchas transistors, resistors, capacitors, and the like, for electricallyisolating active devices in an integrated circuit from one another.

As shown in FIG. 18, a transistor 58″ has been formed on the substrate12″, a BPSG film 60″ having a thickness of about 500 nm has been formedover the transistor, a metal layer 62″ (e.g., aluminum) has been formedon the BPSG film 60″, a titanium nitride (TiN) barrier layer 64″ hasbeen sputtered onto the metal layer 62″, and a wire layer 66″ made ofthe metal layer 62″ and TiN barrier layer 64″ has been formed byetching. Optionally, as shown, a silicon oxide film 68″ has beendeposited onto the wiring layer 66″, for example, by plasma CVD using asilane-based chemistry.

A silicon-containing polymer solution, as exemplified by polysilazane,is spin-coated onto the silicon oxide film 68″ (or directly onto thewiring layer 66″) to form a polysilazane coating layer, which is softbaked to remove the solvent to form a solid-phase polysilazane layer,and then subjected to a low temperature/wet oxidation according to theinvention to oxidize the polysilazane material, resulting in a siliconoxide layer 32 c″, as shown in FIG. 18.

Referring now to FIG. 19, a contact opening 70″ can then be formedthrough the polysilazane-based silicon oxide layer 32 c″ to the wirelayer 66″ by photolithography, a TiN insulating layer 72″ deposited ontothe walls of the opening 70″, and a metal layer 74″ such as tungsten(W), aluminum (Al) or copper (Cu), can be deposited over the TiN layer72″ to fill the opening 70″, thus forming a contact to the underlyingwire layer 66″.

Thus, the silicon oxide layer produced from a polysilazane by theprocess of the invention can be used in various applications andfabrications, such as a fill in a trench isolation structure, as aprotective insulation layer over a semiconductor or integrated circuitdevice, as a planarization layer, or as an inter-layer dielectric, amongother structures and devices.

The process of the invention can also be used with other spin-ondielectrics (SODs) that have a lower oxygen content than SiO₂ such as asiloxane. The SOD material is spin coated as a layer 30 a on thesubstrate 12, dried to form a solid phase dielectric layer 30 b, andthen processed according to the invention using a low temperature, wetoxidation (deionized water/ozone process) as described herein to furtheroxidize the dielectric material to a silicon oxide (primarily silicondioxide, SiO₂) material layer 30 c. Exemplary SOD materials that can beprocessed according to the invention include methyl silsesquioxane,hydrogen silsesquioxane, and silicate, for example.

The process and structures are particularly suitable in the fabricationof various memory circuitry. Examples of memory circuitry includedynamic random-access (DRAM) structures that allow both writing andreading and which memory cells can be accessed in a random orderindependent of physical location, and read-only memory (ROM) devices,such as FLASH memory, that can be selectively erased rapidly through theuse of an electrical erase signal. The process of the invention is alsouseful in fabricating isolation structures in integrated circuit designsthat incorporate field effect transistors (FETs) that include a gateoxide layer formed on a wafer, a gate formed on the gate oxide layer,spacers beside the gate, doped source/drain (S/D) regions on respectivesides of the gate, and shallow trench insulator (STI) regions thatisolate adjacent transistors, including a FinFET device that uses twogates, one on each side of a fin body (i.e., transistor body) tofacilitate scaling of CMOS dimensions.

FIG. 20 is a block diagram of an embodiment of a circuit module 76 inwhich the present invention can be incorporated. Such modules, devicesand systems (e.g., processor systems) incorporating the module aredescribed and illustrated in U.S. Pat. Nos. 6,437,417 (Gilton) and6,465,828 (Agarwal), the disclosures of which are incorporated byreference herein. In brief, two or more dies may be combined into acircuit module 76 to enhance or extend the functionality of anindividual die. Circuit module 76 may be a combination of diesrepresenting a variety of functions, or a combination of dies containingthe same functionality. One or more dies of the circuit module 76 cancontain circuitry, or integrated circuit devices, that includes at leastone polysilazane-based silicon oxide layer in accordance with theembodiments of the present invention. The integrated circuit devices caninclude a memory cell that comprises a silicon oxide layer as discussedin the various embodiments in accordance with the invention.

Some examples of a circuit module 76 include memory modules, devicedrivers (on a BIOS or EPROM), power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Circuit module 76 may be a subcomponentof a variety of electronic systems, such as a clock, a television, acell phone, a personal computer, an automobile, an industrial controlsystem, an aircraft, among others. Circuit module 76 will have a varietyof leads 78 extending therefrom and coupled to dies 80 providingunilateral or bilateral communication and control.

The circuit module can be incorporated, for example, into an electronicsystem that comprises a user interface, for example, a keyboard,monitor, display, printer, speakers, etc. One or more circuit modulescan comprise a microprocessor that provides information to the userinterface, or is otherwise programmed to carry out particular functionsas is known in the art. The electronic system can comprise, for example,a computer system including a processor and a memory system as asubcomponent, and optionally user interface components, and otherassociated components such as modems, device interface cards, etc.Examples of memory circuits include, but are not limited to, DRAM(Dynamic Random Access Memory), SRAM (Static Random Access Memory),Flash memories, a synchronous DRAM such as SGRAM (Synchronous GraphicsRandom Access Memory), SDRAM (Synchronous Dynamic Random Access Memory),SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlinkor Rambus DRAMs and other emerging memory technologies.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

What is claimed is:
 1. A method of forming a silicon oxide material,comprising: filling an opening in a substrate with a solution consistingof polysilazane in a solvent; removing the solvent from the solution toprovide a polysilazane material consisting of silicon, hydrogen andnitrogen elements; and exposing the polysilazane material to water andozone at a temperature of less than about 100° C. without an initialthermal anneal or oxidation at greater than the 100° C. temperature, toconvert the polysilazane material to a silicon oxide material.
 2. Themethod of claim 1, wherein exposing the polysilazane material to waterand ozone comprises exposing the polysilazane material to water andozone at a pressure to about 20 atm.
 3. The method of claim 1, whereinexposing the polysilazane material to water and ozone at a temperatureof less than about 100° C. without an initial thermal anneal oroxidation at greater than the 100° C. temperature comprises producingthe silicon oxide material having an etch rate of less than about 200Å/minute in a fluoride etchant selected from the group consisting of anon-aqueous, fluoride-containing etch solution, an NH₄F based etchreagent, and a solution comprising about 0.01-2% HF.
 4. The method ofclaim 1, wherein exposing the polysilazane material to water and ozonecomprises spraying a solution of water and ozone onto the polysilazanematerial.
 5. The method of claim 4, wherein spraying a solution of waterand ozone onto the polysilazane material comprises spraying the solutionof water and ozone while rotating the polysilazane material on thesubstrate.
 6. A method of forming a silicon oxide material, comprising:partially filling an opening with a material consisting of polysilazane;and wet oxidizing the polysilazane material at a temperature of lessthan about 100° C. without an initial thermal anneal or oxidation atgreater than the 100° C. temperature to produce a silicon oxide materialhaving an oxygen-rich surface and a decreasing oxygen profilethereafter.
 7. The method of claim 6, wherein the oxygen-rich surfaceextends to a depth of up to about 20 nm.
 8. The method of claim 6, wherethe oxygen-rich surface extends to a depth up to about 150 nm.
 9. Themethod of claim 6, wherein the oxygen-rich surface extends to a depth ofat least about 90 nm.
 10. The method of claim 6, wherein wet oxidizingthe polysilazane material at a temperature of less than about 100° C.comprises producing the silicon oxide material having an etch rate ofless than about 200 Å/minute in a fluoride etchant selected from thegroup consisting of a fluoride-containing, non-aqueous, alcohol-basedetch solution, a non-aqueous NH₄F:HF etch solution, and a solutioncomprising about 0.01-2% HF.
 11. A method of forming a silicon oxidematerial, comprising: forming a polysilazane material over a siliconoxide material on a floor and sidewalls of a trench in a substrate; andwet oxidizing the polysilazane material at a temperature of less than100° C. to produce a silicon oxide material having an oxygen-richsurface with at least about 80% of N and H moieties replaced by oxygenas determined by XPS % atomic analysis or SIMS profiling analysis.
 12. Amethod of forming a silicon oxide material, comprising: substantiallyfilling an opening on a substrate with an undensified polysilazaneconsisting of silicon, hydrogen and nitrogen elements; and applying anaqueous ozone solution to the undensified polysilazane material at atemperature of less than about 100° C. to wet oxidize the undensifiedpolysilazane material and form a silicon oxide material without aninitial thermal anneal or oxidation at greater than the temperature. 13.A method of forming an oxide material, comprising: wet oxidizing athickness of a polysilazane material to produce an oxygen-rich surfaceportion and a decreasing oxygen content thereafter; removing a thicknessof the oxygen-rich surface portion of the oxide material; and wetoxidizing an additional thickness of the polysilazane material toincrease the thickness of the oxygen-rich surface portion.
 14. Themethod of claim 13, further comprising, after wet oxidizing theadditional thickness of the polysilazane material, depositing additionalpolysilazane material onto the oxygen-rich surface portion; and wetoxidizing the additional polysilazane material to form an oxygen-richoxide material.
 15. A wet-oxidized polysilazane-based oxide materialfilling an opening in a substrate and having a thickness of about 30-500nm, an oxygen-rich surface comprising N and H moieties at up to 20% to adepth of about 20-150 nm, and a decreasing oxygen profile thereafterwherein the oxygen content decreases from the surface through thethickness of the oxide material, the polysilazane-based oxide materialbeing wet oxidized at a temperature of less than 100° C.
 16. The oxidematerial of claim 15, having a surface composition with a lower oxygencontent than a SiO₂ composition.
 17. The oxide material of claim 15,wherein the oxygen-rich surface extends to a depth up to about 20 nm.18. The oxide material of claim 15, wherein the oxygen-rich surfaceextends to a depth up to about 150 nm.
 19. The oxide material of claim15, wherein the oxygen-rich surface extends to a depth of at least about90 nm.
 20. The oxide material of claim 15, being an isolation structure.21. The oxide material of claim 20, being a shallow trench isolationstructure.
 22. The oxide material of claim 15, being an interlayerdielectric.
 23. The oxide material of claim 22, wherein the interlayerdielectric overlies an active device element.
 24. The oxide material ofclaim 23, wherein the active device element comprises a metal wiring.25. A method of forming a silicon oxide material, comprising: filling atleast a portion of a trench in a substrate with a material consisting ofpolysilazane, the trench having an aspect ratio of at least 5; andexposing the polysilazane material to water and ozone at a temperatureof less than about 100° C. to produce a silicon oxide material without athermal anneal and without a wet oxidation at greater than the 100° C.temperature.
 26. A method of forming a silicon oxide material,comprising: oxidizing a material consisting of an undensifiedpolysilazane in at least a portion of an opening at a temperature ofless than about 100° C. without an initial thermal anneal or oxidationat greater than the 100° C. temperature to produce a silicon oxidematerial having a depth, an oxygen-rich surface comprising N and Hmoieties at up to 20%, and a decreasing oxygen profile thereafterwherein the oxygen content decreases from the surface through the depthof the silicon oxide material; and applying steam to the silicon oxidematerial to increase the oxygen content through the depth of the siliconoxide material.
 27. The method of claim 26, wherein applying steam tothe silicon oxide material comprises reacting hydrogen and oxygen at atemperature of about 125° C.-1,100° C. to form water vapor.
 28. A methodof forming a silicon oxide material, comprising: applying steam in thepresence of ozone at a temperature of about 100° C-200° C. and apressure of 0.5 atm-20 atm and without an initial thermal anneal oroxidation at greater than the 100° C. temperature to a materialconsisting of polysilazane in a trench having an aspect ratio of atleast 5, to produce a silicon oxide material having a depth, anoxygen-rich surface comprising N and H moieties at up to 20%, and adecreasing oxygen profile thereafter wherein the oxygen contentdecreases from the surface through the depth of the silicon oxidematerial.
 29. A polysilazane-based oxide material filling an opening ina substrate and having a thickness of about 30-500 nm, and anoxygen-rich surface comprising N and H moieties at up to 20% to a depthof about 20-150 nm and a decreasing oxygen profile thereafter, thepolysilazane-based oxide material being wet oxidized at a temperature ofless than 100° C.